Integrated circuits (ICs) and the devices therein are at risk of damage due to electrostatic discharge (ESD) events. Accordingly, it is commonplace to provide an ESD clamp (voltage limiting device) across the input and/or other terminals of such devices and IC's.
United States patent application publication 20120295414 describes one simple type of ESD clamp device comprising a bipolar transistor which may be connected across terminals of an IC. When the voltage across the terminals rises beyond a predetermined limit, the bipolar transistor turns on, thereby limiting the voltage across the terminals to a level below that capable of damaging the IC.
U.S. Pat. No. 6,573,566 describes a low voltage-triggered SCR (silicon controlled rectifier) device for protecting against ESD. The disclosed known device uses gate structures formed from gate oxide layers. One drawback of using an oxide layer is a high tunnelling leakage current. Another aspect of this type of known device concerns the triggering of the device by transient voltages. These structures which incorporate gate oxide MOS transistors are activated by capacitance coupling between the drain and gate terminals (with a high resistance between gate and source terminals.) This kind of behaviour can be helpful for electrostatic discharge (ESD) applications but such configurations also tend to be activated by voltage disturbances such as sinusoidal waveforms. This type of behaviour can be undesirable in certain operating circumstances.
United States patent application publication US 20120281329 discloses an ESD device comprising a Zener diode connected between a ground terminal and a node for triggering an SCR circuit which, in turn, comprises an NPN bipolar transistor connected with a PNP bipolar transistor. This known device also includes a diode for suppressing the snapback effect of the SCR. When a transient voltage higher than a normal operating voltage is applied to this known device, a reverse current will pass through the Zener diode if the breakdown voltage of the Zener diode has been set to a voltage that is less than the collector-emitter breakdown voltage of either transistor. As the voltage increases, the device migrates into a bipolar junction transistor mode where the NPN transistor conducts. When the voltage increases further, the SCR is activated and begins to conduct current. The turning on of the SCR causes a drop of the reverse blocking voltage due to snapback. This effect can be suppressed to some extent by connecting one or more diodes in series with the device. However, the snapback voltage of the known device cannot so easily be adjusted owing to its layout. Another drawback of this known arrangement is that an additional layer is required in order to control breakdown voltage of the Zener diode, thus increasing device size. Also, the known arrangement uses a vertical SCR with the (vertical) base of the PNP transistor depending on an N well layer depth and so any adjustment to the collector emitter voltage of the PNP transistor is not easily achieved.